october 1987 revised january 1999 cd4514bc ? cd4515bc 4-bit latched/4-to-16 line decoders ? 1999 fairchild semiconductor corporation ds005994.prf www.fairchildsemi.com cd4514bc? cd4515bc 4-bit latched/4-to-16 line decoders general description the cd4514bc and cd4515bc are 4-to-16 line decoders with latched inputs implemented with complementary mos (cmos) circuits constructed with n- and p-channel enhancement mode transistors. these circuits are prima- rily used in decoding applications where low power dissipa- tion and/or high noise immunity is required. the cd4514bc (output active high option) presents a logi- cal 1 at the selected output, whereas the cd4515bc pre- sents a logical 0 at the selected output. the input latches are rCs type flip-flops, which hold the last input data pre- sented prior to the strobe transition from 1 to 0. this input data is decoded and the corresponding output is acti- vated. an output inhibit line is also available. features n wide supply voltage range: 3.0v to 15v n high noise immunity: 0.45 v dd (typ.) n low power ttl: fan out of 2 compatibility: driving 74l n low quiescent power dissipation: 0.025 m w/package @ 5.0 v dc n single supply operation n input impedance = 10 12 w typically n plug-in replacement for mc14514, mc14515 ordering code: devices also available in tape and reel. specify by appending suffix letter x to the ordering code. connection diagram pin assignments for soic and dip top view order number package number package diagram cd4514bcwm m24b 24-lead small outline integrated circuit (soic), jedec ms-013, 0.300 wide CD4514BCN n24a 24-lead plastic dual-in-line package (pdip), jedec ms-010, 0.600 wide cd4515bcwm m24b 24-lead small outline integrated circuit (soic), jedec ms-013, 0.300 wide cd4515bcn n24a 24-lead plastic dual-in-line package (pdip), jedec ms-010, 0.600 wide
www.fairchildsemi.com 2 cd4514bc ? cd4515bc truth table decode truth table (strobe = 1) x = don't care logic diagram data inputs selected output inhibit d c b a cd4514 = logic 1 cd4515 = logic 0 0 0 0 0 0 s0 0 0 0 0 1 s1 0 0 0 1 0 s2 0 0 0 1 1 s3 0 0 1 0 0 s4 0 0 1 0 1 s5 0 0 1 1 0 s6 0 0 1 1 1 s7 0 1 0 0 0 s8 0 1 0 0 1 s9 0 1 0 1 0 s10 0 1 0 1 1 s11 0 1 1 0 0 s12 0 1 1 0 1 s13 0 1 1 1 0 s14 0 1 1 1 1 s15 1 x x x x all outputs = 0, cd4514 all outputs = 1, cd4515
3 www.fairchildsemi.com cd4514bc ? cd4515bc absolute maximum ratings (note 1) (note 2) recommended operating conditions (note 2) note 1: absolute maximum ratings are those values beyond which the safety of the device cannot be guaranteed. except for operating tempera- ture range they are not meant to imply that the devices should be oper- ated at these limits. the tables of recommended operating conditions and electrical characteristics provide conditions for actual device opera- tion. note 2: v ss = 0v unless otherwise specified. dc electrical characteristics (note 2) cd4514bc, cd4515bc note 3: i oh and i ol are tested one output at a time. dc supply voltage (v dd ) - 0.5v to + 18v input voltage (v in ) - 0.5v to v dd + 0.5v storage temperature range (t s ) - 65 c to + 150 c power dissipation (p d ) dual-in-line 700 mw small outline 500 mw lead temperature (t l ) (soldering, 10 seconds) 260 c dc supply voltage (v dd ) 3v to 15v input voltage (v in ) 0v to v dd operating temperature range (t a ) cd4514bc, cd4515bc - 40 c to + 85 c symbol parameter conditions - 40 c + 25 c + 85 c units min max min typ max min max i dd quiescent device v dd = 5v, v in = v dd or v ss 20 0.005 20 150 m a current v dd = 10v, v in = v dd or v ss 40 0.010 40 300 m a v dd = 15v, v in = v dd or v ss 80 0.015 80 600 m a v ol low level v il = 0v, v ih = v dd , output voltage |i o | < 1 m a v dd = 5v 0.05 0 0.05 0.05 v v dd = 10v 0.05 0 0.05 0.05 v v dd = 15v 0.05 0 0.05 0.05 v v oh high level v il = 0v, v ih = v dd , output voltage |i o | < 1 m a v dd = 5v 4.95 4.95 5.0 4.95 v v dd = 10v 9.95 9.95 10.0 9.95 v v dd = 15v 14.95 14.95 15.0 14.95 v v il low level |i o | < 1 m a input voltage v dd = 5v, v o = 0.5v or 4.5v 1.5 2.25 1.5 1.5 v v dd = 10v, v o = 1.0v or 9.0v 3.0 4.50 3.0 3.0 v v dd = 15v, v o = 1.5v or 13.5v 4.0 6.75 4.0 4.0 v v ih high level |i o | < 1 m a input voltage v dd = 5v, v o = 0.5v or 4.5v 3.5 3.5 2.75 3.5 v v dd = 10v, v o = 1.0v or 9.0v 7.0 7.0 5.50 7.0 v v dd = 15v, v o = 1.5v or 13.5v 11.0 11.0 8.25 11.0 v i ol low level output v dd = 5v, v o = 0.4v 0.52 0.44 0.88 0.36 ma current (note 3) v dd = 10v, v o = 0.5v 1.3 1.1 2.25 0.90 ma v dd = 15v, v o = 1.5v 3.6 3.0 8.8 2.4 ma i oh high level output v dd = 5v, v o = 4.6v - 0.52 - 0.44 - 0.88 - 0.36 ma current (note 3) v dd = 10v, v o = 9.5v - 1.3 - 1.1 - 2.25 - 0.90 ma v dd = 15v, v o = 13.5v - 3.6 - 3.0 - 8.8 - 2.4 ma i in input current v dd = 15v, v in = 0v - 0.3 - 10 - 5 - 0.3 - 1.0 m a v dd = 15v, v in = 15v 0.3 10 - 5 0.3 1.0 m a
www.fairchildsemi.com 4 cd4514bc ? cd4515bc ac electrical characteristics (note 4) all types c l = 50 pf, t a = 25 c, t r = t f = 20 ns unless otherwise specified note 4: ac parameters are guaranteed by dc correlated testing. note 5: c pd determines the no load ac power consumption of any cmos device. for complete explanation, see family characteristics applicati on note, an-90. note 6: capacitance is guaranteed by periodic testing. symbol parameter conditions min typ max units t thl , t tlh transition times v dd = 5v 100 200 ns v dd = 10v 50 100 ns v dd = 15v 40 80 ns t plh , t phl propagation delay times v dd = 5v 550 1100 ns v dd = 10v 225 450 ns v dd = 15v 150 300 ns t plh , t phl inhibit propagation v dd = 5v 400 800 ns delay times v dd = 10v 150 300 ns v dd = 15v 100 200 ns t su setup time v dd = 5v 125 250 ns v dd = 10v 50 100 ns v dd = 15v 38 75 ns t wh strobe pulse width v dd = 5v 175 350 ns v dd = 10v 50 100 ns v dd = 15v 38 75 ns c pd power dissipation capacitance per package (note 5) 150 pf c in input capacitance any input (note 6) 5 7.5 pf
5 www.fairchildsemi.com cd4514bc ? cd4515bc ac test circuit and switching time waveforms figure 1.
www.fairchildsemi.com 6 cd4514bc ? cd4515bc applications two cd4512 8-channel data selectors are used here with the cd4514b 4-bit latch/decoder to effect a complex data routing system. a total of 16 inputs from data registers are selected and transferred via a 3-state data bus to a data distributor for rearrangement and entry into 16 output regis- ters. in this way sequential data can be re-routed or inter- mixed according to patterns determined by data select and distribution inputs. data is placed into the routing scheme via the 8 inputs on both cd4512 data selectors. one register is assigned to each input. the signals on a0, a1 and a2 choose 1-of-8 inputs for transfer out to the 3-state data bus. a fourth signal, labelled dis, disables one of the cd4512 selectors, assuring transfer of data from only one register. in addition to a choice of input registers, 1C16, the rate of transfer of the sequential information can also be varied. that is, if the cd4512 were addressed at a rate that is 8 times faster than the shift frequency of the input registers, the most significant bit (msb) from each register could be selected for transfer to the data bus. therefore, all of the most significant bits from all of the registers can be trans- ferred to the data bus before the next most significant bit is presented for transfer by the input registers. information from the 3-state bus is redistributed by the cd4514b 4-bit latch/decoder. using the 4-bit address, inaCind, the information on the inhibit line can be trans- ferred to the addressed output line to the desired output registers, aCp. this distribution of data bits to the output registers can be made in many complex patterns. for example, all of the most significant bits from the input regis- ters can be routed into output register a, all of the next most significant bits into register b, etc. in this way horizon- tal, vertical, or other methods of data slicing can be imple- mented.
7 www.fairchildsemi.com cd4514bc ? cd4515bc physical dimensions inches (millimeters) unless otherwise noted 24-lead small outline integrated circuit (soic), jedec ms-013, 0.300 wide package number m24b
fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. cd4514bc ? cd4515bc 4-bit latched/4-to-16 line decoders life support policy fairchilds products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com physical dimensions inches (millimeters) unless otherwise noted (continued) 24-lead plastic dual-in-line package (pdip), jedec ms-010, 0.600 wide package number n24a
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